• 30+ mixed signal chips designed/fabricated
• 70 technical publications
• Professional Engineer (PE)
• Senior member of IEEE, ARRL, NSPE, AAAS, SPIE, MRS, Naval Institute
Over 20 years of experience in the semiconductor manufacturing industry.
PhD in EE, minor in Aeronautical Engineering, Space-based Communications
Over a decade of experience at Intel
• Over 18 years of experience in leading edge technology in various engineering disciplines including
design/verification, production and manufacturing, research & development of high speed networking and
communication, quality assurance, integration and segmentation at top global leading semiconductor
companies in Silicon Valley.
• Extensive experience in preparing, and teaching general and highly customized technical courses for new
hired engineers and training overseas engineering staff.
• 35 years of engineering experience in semiconductor design, analysis, measurement, debug, failure analysis and patent infringement analysis. • Prior to freelancing, worked at the memory design firm Mosaid from 1980 to 1994 (64K to 16M DRAM generations) in various roles including designer, design manager, and engineering sales. David now reverseengineers RAM circuits for IP clients, his most recent analysis being a 90 nm embedded DRAM in a leading cellphone device.
• 12+ yrs. diverse experience in advanced IC packaging development, process integration, materials characterization and program management • Authored 32 (issued/pending) patents and 16 technical publications • Certified Electroplater Finisher (CEF) by American Electroplaters and Surface Finishers Society • Knowledge of various characterization/FA techniques & problem solving methodologies 8D, DOE, SPC, FMEA, KT • Well versed in computer applications, highly motivated team leader with strong presentation and interpersonal skills
• Life Senior Member of the IEEE.
• 10 issued/9 pending US patent applications & 6 Publications
• 2015 IEEE Region 6 Central Area Outstanding Engineer Award
• Member of the Executive Steering Committee of the San Francisco Bay Area Nanotechnology Council Chapter, 2005 to present. 2009 & 2014 Chair.
• IEEE SFBA Nanotechnology Council Chapter wins 2014 IEEE NTC Chapter Award.
• Editorial Board Member – International Journal of Humanitarian Technology
• IEEE Global Humanitarian Technology Conference – 2014 Health Track Program Co-Chair
• Listed as a Grant Reviewer for the NSF
Expert in Image Sensor fabrication, operation, devices, packaging
Extensive industry experience spanning multiple applications of Integrated Circuit Technology with an emphasis in fabrication technology
Has contributed in Defense and Aerospace, Semiconductor Device and Manufacturing process development, 3G mobile technology, and Disk Drive Technology
• More than 15 years of experience in embedded systems development (hardware, ASIC/SoC, cloud, and software) for power, performance, and cost-optimized devices
• 26 granted patents (power management, firmware, processing algorithms, bus control in SoC, SSD, and storage)
• 7 presentations, publications, and lectures