Flash memory, EPROM, Cryptography, ASIC, serial ATA, PCI, Cyber security, 802.11ab/g (wireless LAN), 802.3ae(10G Ethernet), Semiconductor failure analysis/Production/Manufacturing
MSEE, 20 yrs of experience, Forensic investigator, lecturer
Intel, AMD, Philips
Embedded DRAM Memory, Semiconductor, Patent infringment, Failure analysis, transistor-level circuit extraction & analysis of memories and mixed-signal (analog/digital)
BSEE, 35+ yrs of experience
Texas Instruments, Chipworks, Mosaid Technologies, Apollo Systems Research Corp, Taeus, Atmos, Nortel, STMicroelectronics, Omicron

Processors/CPUs, PCB, Fab processes; wireless protocols including 802.11, GSM/GPRS/EDGE, Bluetooth; CMOS design, architecture, tape-out and test including memory, mixed signal, and RF; chip reverse engineering; circuit extraction; patent analysis
30+ mixed signal chips designed/fabricated; 70 technical publications; 100+ patents; Professional Engineer; Senior member of IEEE, ARRL, NSPE, AAAS, SPIE, MRS, Naval Institute

Intel, Airfy Communications, Altera

PhD in EE; minor in Aeronautical Engineering; Space-based Communication; over 20 years of experience in the semiconductor manufacturing industry

Advanced IC packaging; Materials characterization; Memory packaging in TSV/3DI, WLP, flip chip, CPB, RDL, BOC, COB, F2F; Strong materials background (corrosion, organic/inorganic hybrid coating, adhesion, solder metallurgy, electroplating)
MS in Material Science, 32 patents, 13 yrs of experience, CEF certification
Micron, Moen, Ralson
DRAM/Flash IC, IC/CAD, pre and post-silicon, IT cloud technology
PhD, 30+ Yrs of experience, Co-Awarded “The Innovator of the Year”, Instructor of Associate & Bachelor Degree Programs
Siemens, Netlist, Ramaxel Technologies, Qimonda/Infineon
Non-Volatile memory, MRAM, Flash, T-RAM, Image sensors, LCD Displays, IC fabrication technology analysis, CMOS Logic, Analog BiCMOS, Photolithography, layer deposition, etching, trench isolation, gate dielectric, polysilicon gates, Cu interconnects, Low K dielectrics, Nanotechnology in physical sciences, Audit IC & MEMS fabrication facilities, processes, & reliability
 Received 2015 IEEE Region 6 Central Area Outstanding Engineer Award.
 Life Senior Member of the IEEE.
 10 issued/9 pending US patent applications & 6 Publications
 2015 IEEE Region 6 Central Area Outstanding Engineer Award
 Member of the Executive Steering Committee of the San Francisco Bay Area Nanotechnology Council Chapter, 2005 to present. 2009 & 2014 Chair.
 IEEE SFBA Nanotechnology Council Chapter wins 2014 IEEE NTC Chapter Award.
 Editorial Board Member – International Journal of Humanitarian Technology
 IEEE Global Humanitarian Technology Conference – 2014 Health Track Program Co-Chair
 Listed as a Grant Reviewer for the NSF
• Texas Instrument • Philips

Expert in Image Sensor fabrication, operation, devices, packaging
Extensive industry experience spanning multiple applications of Integrated Circuit Technology with an emphasis in fabrication technology
Has contributed in Defense and Aerospace, Semiconductor Device and Manufacturing process development, 3G mobile technology, and Disk Drive Technology